1. Field of the Invention
The present invention relates to a ring oscillator circuit. More specifically, the invention relates to a ring oscillator circuit including a ring of cascade-connected delay stages, controlled by a plurality of multiplexers and fed back by a feedback logic gate having an input terminal connected to an output terminal of said ring oscillator circuit, said ring oscillator circuit receiving a control word and emitting on said output terminal a clock signal. The invention relates particularly, but not exclusively, to a ring oscillator circuit for phase locking systems and the following description is made with reference to this field of application for convenience of illustration only.
2. State of the Art
As it is well known, oscillator circuits are usually realized by rings of delay stages connected and driven by multiplexers. A possible application of these ring oscillator circuits is in phase locking systems used in low-voltage power supplies. In particular, these advanced phase locking systems require stable oscillators that can be varied in frequency by a control signal. It is also possible to use ring oscillator circuits in FM demodulators, clock generators for microcontrollers and for serial transmissions.
FIG. 1 shows a ring oscillator circuit realized according to the prior art, globally and schematically indicated with 1. The ring oscillator circuit 1 comprises a plurality of cascade-connected elementary delay stages 3, controlled by a plurality of multiplexers 2 and fed back in a ring 4 by means of a logic gate 5 and a feedback delay stage 6.
For convenience of illustration, FIG. 1 shows a ring oscillator circuit 1 comprising three elementary delay stages 3, indicated with 3-1, 3-2 and 3-3, connected by means of three multiplexers 2, indicated with 2-1, 2-2 and 2-3. A first delay stage 3-1 has an input terminal directly connected to the feedback delay stage 6 and an output terminal connected to a first input terminal of a first multiplexer 2-1, having a second input terminal directly connected to the feedback delay stage 6 by means of a first fast line 7-1.
The first multiplexer 2-1 has also a control terminal receiving a first bit C0 of a control word and an output terminal connected to a second delay stage 3-2. Similarly to the first delay stage 3-1, this second delay stage 3-2 has an output terminal connected to a first input terminal of a second multiplexer 2-2.
The second multiplexer 2-2 has a second input terminal connected by means of a second fast line 7-2 to the output terminal of the first multiplexer 2-1, as well as a control terminal receiving a second bit C1 of the control word and an output terminal connected to a third delay stage 3-3. This third delay stage 3-3 has an output terminal connected to a first input terminal of a third multiplexer 2-3, having in turn a second input terminal connected by means of a third fast line 7-3 to the output terminal of the second multiplexer 2-2, as well as a control terminal receiving a third bit C2 of the control word. The third multiplexer 3-3 has also an output terminal connected to a first input terminal of the logic gate 5, having in turn a second input terminal receiving an external reset signal RESET and an output terminal connected to the feedback delay stage 6.
A clock signal CK is generated on the output terminal of the third multiplexer 2-3, corresponding to an output terminal OUT of the ring oscillator circuit 1. Moreover, the delay stages 3-1, 3-2 and 3-3 comprise an increasing number of elementary delay cells 8, realized by single logic gates (NAND, NOR etc.), or in a ‘standard cell’, not being dedicated to any particular application.
The ring oscillator circuit 1 realized according to the prior art is programmable by changing the control word C0-C2 sent to multiplexers 2. Reference is made to a digitally-controlled oscillator (DCO, or “Digital Controlled Oscillator”), which can be integrated in a completely digital technology and used in applications which cannot use analog circuits, such as completely digital phase locking rings.
The frequency of the ring oscillator circuit 1 is varied by dividing by a programmable number a starting frequency value. In this case, a very high starting frequency value must be provided to obtain good resolution.
The design and realization of a digital divider for a value N is not simple for the frequency values that would be required.
It is also possible to realize the ring oscillator circuit 1 by using tristate elements. In this case it is, however, difficult to obtain high frequency values together with wide frequency variation ranges. Moreover, changing the control word during the normal operation of the ring oscillator circuit 1 leads to the generation of spurious pulses in the ring 4, invalidating the correct operation of the ring oscillator circuit 1.
To avoid the generation of these spurious pulses, the operation of the ring oscillator circuit 1 must be stopped by using the signal RESET to change the control word in stable conditions.
This is a major limitation of the ring oscillator circuit 1 realized according to the prior art, because the circuit shutdown and thus the interruption of the clock signal CK generation is unacceptable in many applications.
The technical problem underlying the present invention is to provide a ring oscillator circuit, having such structural and functional features to overcome the limits still affecting the circuits realized according to the prior art.